1. Field of the Invention
The present invention relates to a semiconductor device applying WLCSP (Wafer Level Chip Size Package) technology and a method for manufacturing the semiconductor device.
2. Description of Related Art
Practical use of WLCSP technology is progressing these days, as a semiconductor device becomes highly efficient and multifunctional. At the semiconductor device applying WLCSP technology, a packaging process is completed in a wafer state including many chips, and a size of each individual chips cut out by dicing becomes a package size.
The semiconductor device applying WLCSP technology, as shown in FIG. 4, includes a semiconductor chip 101, a passivation film 102 covering the surface of the semiconductor chip 101, a polyimide layer 103 formed on the passivation film 102, a rewiring 104 formed on the polyimide layer 103, a sealing resin layer 105 formed on the polyimide layer 103 and the rewiring 104, and a solder ball 106 arranged on the sealing resin layer 105.
In the passivation layer 102, an opening 108 is formed so as to expose a part of an internal wiring of the semiconductor chip 101 as the pad electrode 107. The rewiring 104 is connected to the pad electrode 107 through the through-hole 109 formed so as to penetrate the polyimide layer 103. The rewiring 104 is connected to the solder ball 106 through a post electrode 110 penetrating the sealing resin layer 105. Mounting of this semiconductor device on the print circuit board (electrical and mechanical connection between this semiconductor device and the print circuit board) is accomplished by connecting each of the solder balls 106 to the pad electrode of the print circuit board.
In process of manufacturing the semiconductor device, a semiconductor substrate as a sum of the semiconductor chips is prepared at first. Then the polyimide layer 103 and the rewiring 104 are formed on the passivation film 102 covering the surface of the semiconductor substrate. Then the post electrode 110 is formed on the rewiring 104 at a predetermined position by plating method or the like. Then an epoxy resin, a material of the sealing resin layer 105, is supplied so as to bury the post electrode 110 on the polyimide layer 103 and the rewiring 104.
After the epoxy resin is cured, a surface of the epoxy resin is ground by the grinder and the top surface of the post electrode 110 is exposed from the epoxy resin. Then the solder ball 106 is arranged on the top surface of the post electrode 110. After then, the semiconductor substrate is cut (diced) along a predetermined dicing-line between each semiconductor chip with the passivation film 102 and the sealing resin layer 105. As a result, the semiconductor device shown in FIG. 4 is obtained.
However, the epoxy resin is ground until the top edge face of the post electrode 110 is exposed from the epoxy resin, hence the top surface of the post electrode 110 becomes flush with the surface of the epoxy resin 105 after the grinding process. Therefore, in the cross section orthogonal to the surface of the semiconductor 101, the post electrode 110 includes a corner portion 111 which consists of the top surface and a side surface orthogonal to the top surface. Therefore, due to the post electrode 110 including such a corner portion 111, in the state in which the solder ball 106 is connected to the pad electrode of the print circuit board, the solder ball 106 is intensively received stress from the corner portion 111. By the intensive stress, a crack may form in the solder ball 106.